Efabless Caravel “harness” SoC

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The Efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK. The Caravel harness comprises of base functions supporting IO, power and configuration as well as drop-in modules for a management SoC core, and an approximately 3000um x 3600um open project area for the placement of user IP blocks.

Caravel Floorplan

Fig. 1 Caravel floorplan

This documentation focuses on the IO, protection and housekeeping blocks. The management core SoC has its own [documentation here](https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/)

The Caravel Github repository can be found here: https://github.com/efabless/caravel/

The documentation contains the following chapters:

Caravel harness die

Fig. 6 Caravel harness die (3.2 mm x 5.3 mm)