The RISC-V architecture has a
The best reference for getting the correct cross-compiler version is the PicoRV32 source
in the cliffordwolf/picorv32 repository.
Specifically, see the top-level
README.md file section
Building a pure RV32I Toolchain.
For programming examples specifically for the Caravel chip
(assuming a correct installation of a RISC-V
gcc toolchain as described above),
see efabless/caravel repository.
verilog/dv contains example source code to program the Ravenna chip
along with the header file
defs.h that defines the memory-mapped locations
as described throughout this text.
verilog/dv directory contains a
Makefile that compiles
and runs simulations of a number of test programs that exercise various features of the chip.
Additional documentation exists on the same site for the provided demonstration circuit board and driver software.