QSPI Flash interface

Description

The QSPI flash controller is automatically enabled on power-up, and will immediately initiate a read sequence in single-bit mode with pin flash_io0 acting as SDI (data from flash to CPU) and pin flash_io1 acting as SDO (data from CPU to flash). Protocol is according to, e.g., Cypress S25FL256L.

The initial SPI instruction sequence is as follows:.

Table 12 Initial SPI instruction sequence

0xFF

Mode bit reset

0xAB

Release from deep power-down

0x03

Read w/3 byte address

0x00

Program start address (0x10000000) (3 bytes) (upper byte is ignored)

0x00

0x00

The QSPI flash continues to read bytes, either sequentially on the same command, or issuing a new read command to read from a new address.

reg_spictrl

QSPI control register

The behaviour of the QSPI flash controller can be modified by changing values in the register below:

Base address: 0x2d000000

Table 13 reg_spictrl register description

Mask bit

Default

Description

31

1

QSPI flash interface enable

22-20

0

Access mode (including DDR enable, QSPI enable, CRM enable) (see reg_spictrl Access mode bit values)

19-16

8

Dummy clock cycle count / Read latency cycles

11-8

0

Bit-bang OE_FLASH_IO[3:0] I/O output enable

5

0

Bit-bang FLASH_CSB chip select bit

4

0

Bit-bang FLASH_CLK serial clock line

3-0

0

Bit-bang FLASH_IO[3:0] data bits

QSPI access modes

Table 14 reg_spictrl Access mode bit values

0

000

Single bit per clock

1

001

Single bit per clock (same as 0)

All additional modes (QSPI dual and quad modes) cannot be used, as the management SoC only has pins for data lines 0 and 1.

The SPI flash can be accessed by bit banging when the enable is off. To do this from the CPU, the entire routine to access the SPI flash must be read into SRAM and executed from the SRAM.

Note

To sum up, the DDR enable, QSPI enable and CRM enable bits cannot be used due to the limited number of data pins.