SPI Controller
This section describes the SPI configuration registers.
reg_spi_config
Base address: 0x24000000
Bit |
Name |
Values |
|---|---|---|
15 |
Housekeeping |
0 - SPI controller connected to external pins 1 - SPI controller connected directly to housekeeping SPI |
14 |
SPI interrupt enable |
0 - interrupt disabled 1 - interrupt enabled ( IRQ channel 9 ) |
13 |
SPI system enable |
0 - SPI disabled 1 - SPI enabled |
12 |
stream |
0 - apply/release CSB separately for each byte 1 - apply CSB until stream bit is cleared (manually) |
11 |
mode |
0 - read and change data on opposite SCK edges (default) 1 - read and change data on the same SCK edges |
10 |
invert SCK |
0 - normal SCK (default) 1 - inverted SCK |
9 |
invert CSB |
0 - normal CSB (low is active, default) 1 - inverted CSB (high is active) |
8 |
MLB |
0 - MSB first 1 - LSB first |
7-0 |
prescaler |
count (in controller clock cycles) of 1/2 SCK cycle (default value 2). Clock rate formula: SPI clock rate = 2 * core_clock / (prescaler + 1) |
Note
All configuration bits other than the prescaler default to value zero.
reg_spi_data
Base address: 0x24000004
The byte at 0x24000004 holds the SPI data (either read or write).
Reading to and writing from the SPI controller is simply a matter of setting the required values in the configuration register, and writing values to or reading from reg_spi_data.
The protocol is similar to the UART.
A write operation will stall the CPU if an incomplete SPI transmission is still in progress.
Reading from the SPI will also stall the CPU if an incomplete SPI transmission is still in progress. There is no FIFO buffer for data. Therefore SPI reads and writes are relatively expensive operations that tie up the CPU, but will not lose or overwrite data.
Note
There is no FIFO associated with the SPI controller.