General Purpose Input/Output
The GPIO pin is a single assignable general-purpose digital input or output that is available only to the management SoC and cannot be assigned to the user project area. On the test board provided with the completed user projects, this pin is used to enable the voltage regulators generating the user area power supplies.
The basic function of the GPIO is illustrated in GPIO channel structure. All writes to reg_gpio_data are registered. All reads from reg_gpio_data are immediate.
Register descriptions
C header name |
Address |
Description |
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GPIO input/output (low bit) GPIO output readback (16th bit) |
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GPIO output enable (0 = output, 1 = input) |
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GPIO pullup enable (0 = none, 1 = pullup) |
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GPIO pulldown enable (0 = none, 1 = pulldown) |
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PLL clock output destination (low bit) |
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Trap output destination (low bit) |
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IRQ 7 input source (low bit) |
Note
In the registers description below, each register is shown as 32 bits corresponding to the data bus width of the wishbone bus. Depending on the instruction and data type, the entire 32-bit register can be read in one instruction, or one 16-bit word, or one 8-bit byte.
reg_gpio_data
Base address: 0x21000000
Writing to the address low bit always sets the registered value at the GPIO.
Writing to address bit 16 has no effect.
Reading from the address low bit reads the value at the chip pin.
Reading from address bit 16 reads the value at the multiplexer output (see GPIO channel structure).
reg_gpio_ena
Base address: 0x21000004
Bit 0 corresponds to the GPIO channel enable.
Bit value 1 indicates an output channel; 0 indicates an input.
reg_gpio_pu
Base address: 0x21000008
Bit 0 corresponds to the GPIO channel pull-up state.
Bit value 1 indicates pullup is active; 0 indicates pullup is inactive.
reg_gpio_pd
Base address: 0x2100000c
Bit 0 corresponds to the GPIO channel pull-down state.
Bit value 1 indicates pullup is active; 0 indicates pulldown is inactive.
reg_pll_out_dest
Base address: 0x2f000000
The PLL clock (crystal oscillator clock multiplied up by PLL) can be viewed on the GPIO pin. The GPIO pin cannot be used as general-purpose I/O when selected for PLL clock output.
The low bit of this register directs the output of the core clock to the GPIO channel, according to the reg_pll_out_dest register settings.
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Clock output directed to this channel |
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(none) |
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Core PLL clock to GPIO output |
Note
High rate core clock (e.g. 80MHz) may be unable to generate a full swing on the GPIO output, but is detectable.
reg_trap_out_dest
Base address: 0x2f000004
The CPU fault state (trap) can be viewed at the GPIO pin as a way to monitor the CPU trap state externally. The low bit of this register directs the output of the processor trap signal to the GPIO channel, according to the reg_trap_out_dest register settings.
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Trap signal output directed to this channel |
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(none) |
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GPIO |
reg_irq7_source
Base address: 0x2f000008
The GPIO input can be used as an IRQ event source and passed to the CPU through IRQ channel 7 (see Interrupts (IRQ)). When used as an IRQ source, the GPIO pin must be configured as an input. The low bit of this register directs the input of the GPIO to the processor’s IRQ7 channel, according to the reg_irq7_source register settings.
Register byte |
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This channel directed to IRQ channel 7 |
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0 |
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(none) |
1 |
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GPIO |
User project area GPIO
User project area GPIO mprj_io[37:0]
configure registers
Each of 38 mprj_io
GPIOs has a configuration register.
User project area GPIO |
Address |
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Mask bit |
Default |
Description |
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10-12 |
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Digital mode |
9 |
TODO |
input voltage trip point select |
8 |
0 |
slow slew (0 - fast slew, 1 - slow slew) |
7 |
TODO |
analog bus polarity |
6 |
TODO |
analog bus select |
5 |
TODO |
analog bus enable (0 - disabled, 1 - enabled) |
4 |
TODO |
IB mode select |
3 |
0 |
input disable (0 - input enabled, 1 - input disabled) |
2 |
0 |
hold override value (value is the value during hold mode) |
1 |
1 |
output disable (0 - output enabled, 1 - output disabled) |
0 |
1 |
management control enable (0 - user control, 1 - management control) |