Pinout description

This section describes lists the pinout for the SoC, and provides the description for pins.

Ball assignment (6x10 WLCSP)

Fig. 2 Ball assignment (6x10 WLCSP)

Pinout (6x10 WLCSP)

Table 1 Pinout

	F	E	D	C	B	A
1	mprj_io[15]	mprj_io[16]	mprj_io[18]	mprj_io[19]	mprj_io[21]	mprj_io[23]
2	vccd1	mprj_io[14]	mprj_io[17]	mprj_io[20]	mprj_io[22]	vccd2
3	mprj_io[12]	mprj_io[11] flash2_io[1]	mprj_io[13]	mprj_io[24]	vssa2	mprj_io[25]
4	mprj_io[10] flash2_io[0]	mprj_io[9] flash2_sck	vdda1	vddio	mprj_io[26]	mprj_io[27]
5	mprj_io[8] flash2_csb	mprj_io[7] irq	vssio vssa vssd	vssio vssa vssd	mprj_io[28]	mprj_io[29]
6	vssd1	vssa1	vssio vssa vssd	vssio vssa vssd	mprj_io[30]	mprj_io[31]
7	mprj_io[6] ser_tx	mprj_io[5] ser_rx	mprj_io[0] JTAG	vdda2	vssd2	mprj_io[32]
8	mprj_io[4] SCK	mprj_io[3] CSB	flash_clk	mprj_io[33]	mprj_io[34]	mprj_io[35]
9	mprj_io[2] SDI	mprj_io[1] SDO	flash_io[1]	clock	mprj_io[36]	mprj_io[37]
10	vdda	gpio	flash_io[0]	flash_csb	resetb	vccd

Pin description (6x10 WLCSP)

Table 2 Pin description

Pin #	Name	Type	Summary description
A9, B9, A8, B8, C8, A7, A6, B6, A5, B5, A4, B4, A3, C3, A1, B2, B1, C2, C1, D1, D2, E1, F1, E2, D3, F3, E3, F4, E4, F5, E5, F7, E7, F8, E8, F9, E9, D7	mprj_io[37:0]	Digital I/O	General purpose configurable digital I/O with pullup/pulldown, input or output, enable/disable, analog output, high voltage output, slew rate control. Shared between the user project area and the management SoC.
D8	flash_clk	Digital out	Flash SPI clock
C10	flash_csb	Digital out	Flash SPI chip select
D9, D10	flash_io[1:0]	Digital I/O	Flash SPI data input/output
C9	clock	Digital in	External CMOS 3.3V clock source
B10	resetb	Digital in	SoC system reset (sense inverted)
E9	SDO	Digital out	Housekeeping serial interface data output
F9	SDI	Digital in	Housekeeping serial interface data input
E8	CSB	Digital in	Housekeeping serial interface chip select
F8	SCK	Digital in	Housekeeping serial interface clock
F7	ser_tx	Digital out	UART transmit channel
E7	ser_rx	Digital in	UART receive channel
E5	irq	Digital in	External interrupt
E10	gpio	Digital I/O	Management GPIO/user power enable
D7	JTAG	Digital I/O	JTAG system access
F5	flash2_csb	Digital out	User area QSPI flash enable (sense inverted)
E4	flash2_sck	Digital out	User area QSPI flash clock
E3, F4	flash2_io[1:0]	Digital I/O	User area QSPI flash data
F9	spi_sdo	Digital out	Serial interface controller data output
F8	spi_sck	Digital out	Serial interface controller clock
E8	spi_csb	Digital out	Serial interface controller chip select
E9	spi_sdi	Digital in	Serial interface controller data input
C4	vddio	3.3V Power	ESD and padframe power supply
F10	vdda	3.3V Power	Management area power supply
A10	vccd	1.8V Power	Management area digital power supply
C5, C6, D5, D7	vssio/vssa/vssd	Ground	ESD, padframe, and management area ground
D4	vdda1	3.3V Power	User area 1 power supply
F2	vccd1	1.8V Power	User area 1 digital power supply
E6	vssa1	Ground	User area 1 ground
F6	vssd1	Ground	User area 1 digital ground
C7	vdda2	3.3V Power	User area 2 power supply
A2	vccd2	1.8V Power	User area 2 digital power supply
B3	vssa2	Ground	User area 2 ground
B7	vssd2	Ground	User area 2 digital ground

Table 3 Package physical measurements

Standard package	WLCSP (bump bond)
Package size	3.2 mm x 5.3 mm
Bump pitch	0.5 mm