Caravel Harness
latest
Caravel Architecture
Quick Start for User Projects
Required Directory Structure
Additional Material
Repositories and versions to use
User project quick start guide
Using OpenLANE to Harden Your Design
Pinout description
General Purpose Input/Output
Housekeeping SPI
QSPI Flash interface
External clock
UART interface
SPI Controller
Counter-Timers
Interrupts (IRQ)
SRAM
Programming
Memory Mapped I/O summary
Supplementary figures
GPIO pads - management and user IO
GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
GPIO pad structure - all pads except 0 and 1
Die arrangement and pads
Die voltage clamp arrangement
Die plot
Die to WLCSP bond plan
Power domain splits
PCB example route pattern
Absolute maximum ratings
References
Further work
Caravel Harness
Supplementary figures
Edit on GitHub
Supplementary figures
GPIO pads - management and user IO
GPIO pad structure - pads 0 (JTAG) and 1 (SDO)
GPIO pad structure - all pads except 0 and 1
Die arrangement and pads
Die voltage clamp arrangement
Die plot
Die to WLCSP bond plan
Power domain splits
PCB example route pattern