Efabless Caravel “harness” SoC

Introduction

The Efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK. The Caravel harness comprises of base functions supporting IO, power and configuration as well as drop-in modules for a management SoC core, and an approximately 3000um x 3600um open project area for the placement of user IP blocks.

Fig. 1 Caravel floorplan

This documentation focuses on the IO, protection and housekeeping blocks. The management core SoC has its own [documentation here](https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/)

The Caravel Github repository can be found here: https://github.com/efabless/caravel/

The documentation contains the following chapters:

• Description contains the general information about the Efabless Caravel “harness” SoC,

• Caravel Architecture contains the general information about how to use the Efabless Caravel “harness” SoC,

• Repositories and versions to use contains the tool versions prefered for usage with the current Efabless Caravel “harness” SoC,

• User project quick start guide contains a guide on how to get quickly started with using Efabless Caravel “harness” SoC without many details,

• Using OpenLANE to Harden Your Design contains information on how to build your user project with OpenLANE inside the Efabless Caravel “harness” SoC,

• Pinout description describes the pinout of the SoC,

• General Purpose Input/Output describes GPIO and its registers,

• Housekeeping SPI describes the SPI responder that can be accessed from a remote host,

• QSPI Flash interface describes the QSPI flash controller,

• External clock describes the source external clock for the CPU,

• UART interface describes the UART interface,

• SPI Controller describes the SPI configuration,

• Counter-Timers describes two counter/timers blocks,

• Interrupts (IRQ) describes the interrupts,

• SRAM describes management and storage area SRAM,

• Programming shows how to get started with programming on Caravel chip,

• Memory Mapped I/O summary lists the memory mapped I/O registers by address,

• Supplementary figures provides supplementary internal structure and die arrangement figures

• Absolute maximum ratings lists the parameters and their ranges at which the device operates correctly,

• References contains list of references,

• Further work lists things to be added to the documentation.

Fig. 6 Caravel harness die (3.2 mm x 5.3 mm)