Efabless Caravel “harness” SoC

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Introduction

The efabless Caravel chip is a ready-to-use test harness for creating designs with the Google/Skywater 130nm Open PDK. The Caravel harness comprises a small RISC-V microprocessor based on the simple 2-cycle PicoRV32 RISC-V core implementing the RV32IMC instruction set (see riscv.org page), a 32-bit wishbone bus, and an approximately 2.8mm x 2.8mm open area for the placement of user IP blocks.

Caravel management SoC simplified block diagram

Fig. 1 Caravel management SoC simplified block diagram


The Github Repo could be found here: https://github.com/efabless/caravel/

The documentation contains the following chapters:

Caravel harness die

Fig. 6 Caravel harness die (3.2 mm x 5.3 mm)